View HT82K74E_4698682.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HT82K74E/HT82K74EE 27MHz Keyboard/ Mouse TX 8-Bit MCU
Technical Document
* Application Note - HA0075E MCU Reset and Oscillator Circuits Application Note
Features
* Operating voltage: * 1288 bits data EEPROM for HT82K74EE * One external crystal (27MHz) to supply
fSYS= 27MHz: 3.0V~3.3V for crystal mode
* Program Memory: 2K15 bits * Data Memory: 968 bits * 36 bidirectional I/O lines, with pull-high options * Watchdog Timer function * Single 16-bit internal timer with overflow interrupt
microcontroller system clock
* 63 powerful instructions * All instructions executed in one or two machine
cycles
* Low voltage reset function * Crystal oscillator which built-in capacitor value can
and timer input
* Power down and wake-up functions to reduce
configure by firmwave OSCC register
* Two bit to define microcontroller system clock
power consumption
* 4-level subroutine nesting * Bit manipulation instruction * Table read instructions * Built-in DC/DC to provide stable (2.8V, 3.0V, 3.3V
(fSYS/1, fSYS/4, fSYS/8, fSYS/16)
* HT82K74E:
28-pin SSOP, 32-pin QFN and 48-pin SSOP/LQFP packages
* HT82K74EE:
use configuration option) DC_DC 3.0V with error 0.1V
* 2.2V/2.0V with 0.1V tolerance or 1.8V Low battery
28-pin SSOP and 48-pin SSOP/LQFP packages
detector with internal bit set, it detects the BAT-in input voltage
General Description
The device is an 8-bit high performance, RISC architecture microcontroller devices specifically designed for multiple I/O control product applications. The advantages of low power consumption, I/O flexibility, timer functions, Power Down and wake-up functions, Watchdog timer, motor driving, industrial control, consumer products, subsystem controllers, etc. There are two dice in the HT82K74EE package: one is the HT82K74E MCU, the other is a 1288 bits EEPROM used for data memory purpose. The two dice are wire-bonded to form HT82K74EE
Block Diagram
S ta c k
EEPROM D a ta M e m o ry
OTP P ro g ra m M e m o ry
RAM D a ta M e m o ry
R eset C ir c u it 8 - b it R IS C C o re
W a tc h d o g T im e r O s c illa to r W a tc h d o g T im e r V o lta g e D e te c to r D C /D C
I/O P o rts
1 6 - b it T im e r
Power A m p lifie r
C ry s ta l O s c illa to r
In te rru p t C o n tr o lle r
Rev. 1.00
1
December 15, 2009
HT82K74E/HT82K74EE
Pin Assignment
PB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PA7 PA6 PA5 PA4 PA3 P A 2 /T M R PA1 PA0 VSS PA7 PA6 PA5 PA4 PA3 P A 2 /T M R PA1 PA0 PC1 PC0 P D 3 /Z B P D 2 /Z A P D 1 /V B P D 0 /V A 9 10 11 12 13 14 8 7 6 5 4 3 2 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PB0 PB1 PB2 PB3 LX VSSLX B A T _ IN VDD RF_O U T VSS OSC1 OSC2 VDD RESB PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 P D 3 /Z B P D 2 /Z A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 PB1 PB2 PB3 PB4 PB5 PB6 PB7 LX VSSLX B A T _ IN VDD RF_O U T VSS OSC1 OSC2 VDD PE0 PE1 VSS RES PE2 PE3 P D 0 /V A P D 1 /V B PB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PA7 PA6 PA5 PA4 PA3 P A 2 /T M R PA1 PA0 VSS PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 P D 3 /Z B P D 2 /Z A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 PB1 PB2 PB3 PB4 PB5 PB6 PB7 LX VSSLX B A T _ IN VDD RF_O U T VSS OSC1 OSC2 VDD P E 0 /S D A P E 1 /S C L VSS RES PE2 PE3 P D 0 /V A P D 1 /V B
H T 8 2 K 7 4 E /H T 8 2 K 7 4 E E 2 8 S S O P -A
H T82K 74E 4 8 S S O P -A
H T82K 74EE 4 8 S S O P -A
PB6 PB5 PB4 PB3 PB2 PB1 PB0 PA7 PA6 PA5 PA4 PA3
P P P P P P P A 2 /T M
32 31 30 29282726 25 1 2 3 4 5 6 7 8 9 1011 1213 1415 16
PA1 PA0 PC5 PC4 PC3 PC2 PC1 PC0
24 23 22
H T82K 74E 3 2 Q F N -A
21 20 19 18 17
VSS BAT VDD RF_ VSS OSC OSC VDD
LX _ IN OUT 1 2
P A 2 /T M PA PA VS PC PC PC PC PC PC PC PC
R 1 S 0
1 2 3 4 7 6 5 4 3 2 1 0 9 8 7 6 5
48 47 46 45 44 43 42 41 40 39 38 37
36 35 34 33 32
H T82K 74E 4 8 L Q F P -A
31 30 29 28 27
10 11
26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 VSS RES PE2 PE3 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
PB7 LX VSS BAT VDD RF_ VSS OSC OSC VDD PE0 PE1
P A 2 /T M PA PA VS PC PC PC PC PC PC PC PC
R 1 S 0
1 2 3 4 7 6 5 4 3 2 1 0 9 8 7 6 5
48 47 46 45 44 43 42 41 40 39 38 37
A3
A4
A5
A6
A7
LX B7
R 10 11
LX _ IN OUT 1 2
26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 VSS RES PE2 PE3 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 /V A /V B /Z A /Z B
RES PD1 PD2 PD3 PD4 PD5 PD6 PD7 H T82K 74EE 4 8 L Q F P -A B /V B /Z A /Z B PB6 PB5 PB4 PB3 PB2 PB1 PB0 PA7 PA6 PA5 PA4 PA3 36 35 34 33 32 31 30 29 28 27 PB7 LX VSS BAT VDD RF_ VSS OSC OSC VDD PE0 PE1 LX _ IN OUT 1 2 /S D A /S C L
/V A /V B /Z A /Z B
Rev. 1.00
2
December 15, 2009
HT82K74E/HT82K74EE
Pin Description
Pin Name PA0~PA1 PA2/TMR PA3~PA7 I/O Options Description Bidirectional 8-bit input/output port. Each pin can be configured as a wake-up input (both falling and rising edge) by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors. PA2 is shared with the external timer input pin TMR. Bidirectional 8-bit input/output port. Each nibble, PB0~PB3 and PB4~PB7, pins can be configured as wake-up inputs (both falling and rising edge) by configuration options. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors. Bidirectional 8-bit input/output port. Each nibble, PC0~PC3 and PC4~PC7, pins can be configured as wake-up inputs (both falling and rising edge) by configuration options. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors. Bidirectional 8-bit input/output port. Each nibble, PD0~PD3 and PD4~PD7, pins can be configured as wake-up inputs (both falling and rising edge) by configuration options. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors. PD0 and PD1 are shared with the VA and VB pins. PD2 and PD3 are shared with the ZA and ZB pins. Bidirectional 4-bit input/output port. PE0~PE3 pin can be configured as wake-up inputs (both falling and rising edge) by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors. For HT82K74EE PE0 and PE1 are shared with the SDA and SCL lines respectively and not bonded to external pins. OSC1, OSC2 are connected to an external 27MHz crystal/ resonator for the internal system clock. Negative power supply, ground Schmitt trigger reset input. Active low Positive power supply Battery input DC/DC LX switch DC/DC ground RF power amplifier output pin
I/O
Pull-high Wake-up
PB0~PB7
I/O
Pull-high Wake-up
PC0~PC7
I/O
Pull-high Wake-up
PD0/VA PD1/VB PD2/ZA PD3/ZB PD4~PD7
I/O
Pull-high Wake-up
PE0~PE3
I/O
Pull-high Wake-up
OSC1 OSC2 VSS RES VDD BAT_IN LX VSSLX RF_OUT
I O 3/4 I 3/4 I I I O
3/4 3/4 3/4 3/4 3/4 3/4 3/4 Full Power/ Half Power
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ..............................................................150mA Total Power Dissipation .....................................500mW Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.00
3
December 15, 2009
HT82K74E/HT82K74EE
D.C. Characteristics
Symbol VDD VOUT IDD ISTB VIL1 VIH1 VIL2 VIH2 VLVR IOL1 IOH1 RPH1 BAT-in Parameter Operating Voltage DC-DC Operating Voltage Operating Current (Crystal OSC) Standby Current Input Low Voltage for I/O (Schmitt Trigger) Input High Voltage for I/O (Schmitt Trigger) Input Low Voltage (RES) Input High Voltage (RES) Low Voltage Reset Other I/O Pins Sink Current Other I/O Pins Source Current Other Pins Internal Pull-high Resistance Input Voltage Test Conditions VDD 3/4 3/4 3V 3/4 3/4 3/4 3/4 3/4 3/4 3V 3V 3V 3/4 VOL=0.1VDD VOH=0.9VDD 3/4 3/4 Conditions Others fSYS=27MHz No load, fSYS= 27MHz No load, system HALT WDT disable, LVR disable 3/4 3/4 3/4 3/4 3/4 Min. 2.0 2.8 3/4 3/4 0 0.7VDD 0 0.9VDD 3.5 4 -2.5 10 2 Typ. 3/4 3/4 3 3/4 3/4 3/4 3/4 3/4 3.8 3/4 -4.5 30 2.8 Max. 3.3 3.3 6 20 0.3VDD VDD 0.3VDD VDD 4.0 3/4 3/4 50 3.3 Ta=25C Unit V V mA mA V V V V V mA mA kW V
A.C. Characteristics
Test Conditions Symbol fSYS tRCSYS tWDT tSST Parameter VDD System Clock Watchdog OSC Period Watchdog Time-out Period with 6-stage Prescaler System Start-up Timer Period 3/4 3V 3V 3/4 3/4 3/4 3/4 WDTS=1 3/4 3/4 3/4 3/4 Conditions 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0.25 10 27 71 4.57 1024 10 1.00 3/4 3/4 3/4 3/4 3/4 3/4 2.00 3/4 Min. Typ. Max.
Ta=25C Unit MHz ms ms tSYS ms ms ms
tOSTSETUP Crystal Setup tLVR tRES Low Voltage Width to Reset External Reset Low Pulse Width
Note: tSYS=1/fSYS
Rev. 1.00
4
December 15, 2009
HT82K74E/HT82K74EE
RF Characteristics
Test Conditions Symbol Parameter VDD PRF Maximum Output Power (Load impedance is 50W) 20dB Bandwidth for Modulated Carrier (3Kbps) 1st Adjacent Channel Transmit Power 50kHz 2nd Adjacent Channel Transmit Power 100kHz 3/4 3/4 3/4 3/4 Conditions PWRAMP option selected Half PWRAMP option selected Full 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 -3 0 6 3/4 3/4 3/4 3/4 3/4 -30 -40 dBm dBm kHz dBm dBm Min. Typ. Max. Unit Ta=25C
PBW PRF1 PRF2
DC_AC Power-on Reset AC/DC Characteristics
Test Conditions Symbol IPOR RSR_POR VPOR_MAX Parameter VDD Operating Current VDD Rise Rate to Ensure Power-on Reset Maximum VDD Start Voltage to Ensure Power-on Reset 2.0V~ 3.3V 3/4 3/4 Conditions 3/4 Without 0.1mF between VDD and VSS Without 0.1mF between VDD and VSS Without 0.1mF between VDD and VSS With 0.1mF between VDD and VSS 3/4 0.05 0.9 2 10 3/4 3/4 3/4 3/4 3/4 0.7 3/4 1.5 3/4 3/4 Min. Typ. Max.
Ta=25C Unit mA V/ms V ms ms
tPOR
Power-on Reset Low Pulse Width
3/4
Rev. 1.00
5
December 15, 2009
HT82K74E/HT82K74EE
EEPROM A.C. Characteristics
Standard Mode* Symbol fSK tHIGH tLOW tr** tf** tHD:STA tSU:STA tHD:DAT tSU:DAT tSU:STO tAA tBUF tSP tWR Note: Parameter Clock Frequency Clock High Time Clock Low Time SDA and SCL Rise Time SDA and SCL Fall Time START Condition Hold Time START Condition Setup Time Data Input Hold Time Data Input Setup Time STOP Condition Setup Time Output Valid from Clock Bus Free Time Input Filter Time Constant (SDA and SCL Pins) Write Cycle Time Remark Min. 3/4 3/4 3/4 3/4 3/4 After this period the first clock pulse is generated Only relevant for repeated START condition 3/4 3/4 3/4 3/4 Time in which the bus must be free before a new transmission can start Noise suppression time 3/4 3/4 4000 4700 3/4 3/4 4000 4000 0 200 4000 3/4 4700 3/4 3/4 Max. 100 3/4 3/4 1000 300 3/4 3/4 3/4 3/4 3/4 3500 3/4 100 5 kHz ns ns ns ns ns ns ns ns ns ns ns ns ms Unit Ta=25C
These parameters are periodically sampled but not 100% tested * The standard mode means VDD=2.2V to 3.3V ** For related timing, refer to timing diagrams in the EEPROM Data Memory section
Rev. 1.00
6
December 15, 2009
HT82K74E/HT82K74EE
System Architecture
A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to the internal system architecture. The devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all operations of the instruction set. It carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O control system with maximum reliability and flexibility. Clocking and Pipelining The main system clock, derived from either a Crystal/Resonator or RC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as JMP or CALL that demand a jump to a non-consecutive Program Memory address. It must be noted that only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by user.
O s c illa to r C lo c k ( S y s te m C lo c k ) P h a s e C lo c k T 1 P h a s e C lo c k T 2 P h a s e C lo c k T 3 P h a s e C lo c k T 4 P ro g ra m C o u n te r PC PC+1 PC+2
P ip e lin in g
F e tc h In s t. (P C ) E x e c u te In s t. (P C -1 )
F e tc h In s t. (P C + 1 ) E x e c u te In s t. (P C )
F e tc h In s t. (P C + 2 ) E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
1 2 3 4 5 6 D ELAY: : :
M O V A ,[1 2 H ] C ALL D ELAY C P L [1 2 H ]
F e tc h In s t. 1
E x e c u te In s t. 1 F e tc h In s t. 2 E x e c u te In s t. 2 F e tc h In s t. 3 F lu s h P ip e lin e F e tc h In s t. 6 E x e c u te In s t. 6 F e tc h In s t. 7
NOP
Instruction Fetching
Rev. 1.00
7
December 15, 2009
HT82K74E/HT82K74EE
When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. The lower byte of the Program Counter is fully accessible under program control. Manipulating the PCL might cause program branching, so an extra cycle is needed to pre-fetch. Further information on the PCL register can be found in the Special Function Register section. Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack has 4 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, SP, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching.
P ro g ra m T o p o f S ta c k S ta c k L e v e l 1 S ta c k P o in te r B o tto m o f S ta c k S ta c k L e v e l 2 S ta c k L e v e l 3 S ta c k L e v e l 4 P ro g ra m M e m o ry C o u n te r
Arithmetic and Logic Unit - ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions:
* Arithmetic operations: ADD, ADDM, ADC, ADCM,
SUB, SUBM, SBC, SBCM, DAA
Program Counter Bits Mode b10 Initial Reset Timer/Event Counter Overflow Skip Loading PCL Jump, Call Branch Return from Subroutine PC10 #10 S10 PC9 #9 S9 PC8 #8 S8 @7 #7 S7 0 0 b9 0 0 b8 0 0 b7 0 0 b6 0 0 b5 0 0 b4 0 0 b3 0 1 b2 0 0 b1 0 0 b0 0 0
Program Counter + 2 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0
Program Counter Note: PC10~PC8: Current Program Counter bits @7~@0: PCL bits #10~#0: Instruction code address bits S10~S0: Stack register bits 8 December 15, 2009
Rev. 1.00
HT82K74E/HT82K74EE
* Logic operations: AND, OR, XOR, ANDM, ORM, * Location 008H
XORM, CPL, CPLA
* Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
RLC
* Increment and Decrement INCA, INC, DECA, DEC * Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,
This vector is used by the timer/event counter. If a counter overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full.
* Table location
SIZA, SDZA, CALL, RET, RETI
Program Memory
The Program Memory is the location where the user code or program is stored. The device is supplied with One-Time Programmable, OTP, memory where users can program their application code into the device. By using the appropriate programming tools, OTP devices offer users the flexibility to freely develop their applications which may be useful during debug or for products requiring frequent upgrades or program changes. OTP devices are also applicable for use in applications that require low or medium volume production runs. Structure The Program Memory has a capacity of 2K15 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by separate table pointer registers.
000H 004H 008H D e v ic e In itia liz a tio n P r o g r a m
Any location in the program memory can be used as look-up tables. There are three methods to read the ROM data by two table read instructions: TABRDC and TABRDL, transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H).
The three methods are shown as follows: The instructions TABRDC [m] (the current page, one page=256words), where the table locations is defined by TBLP (07H) in the current page. And the TBHP function selected via a configuration option is disabled (default). The instruction TABRDC [m], where the table location is defined by registers TBLP (07H) and TBHP (01FH). And the TBHP function selected via a configuration option is enabled. The instructions TABRDL [m], where the table locations is defined by Registers TBLP (07H) in the last page (700H~7FFH).
T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e P ro g ra m M e m o ry L o o k - u p T a b le ( 2 5 6 w o r d s )
n00H nFFH
7FFH
L o o k - u p T a b le ( 2 5 6 w o r d s ) 1 5 b its N o t Im p le m e n te d
Program Memory Structure Special Vectors Within the Program Memory, certain locations are reserved for special usage such as reset and interrupts.
* Location 000H
This vector is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution.
Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, and the remaining 1-bit words are read as 0. The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP, TBHP) is a read/write register (07H, 1FH), which indicates the table location. Before accessing the table, the location must be placed in the TBLP and TBHP (If the TBHP function selected via a configuration option is disabled, the value in TBHP has no effect). The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt should be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions require two cycles to complete the operation. These areas may function as normal program memory depending on the requirements. Once TBHP is enabled, the instruction TABRDC [m] reads the ROM data as defined by TBLP and TBHP value. Otherwise, the TBHP function selected via a configuration option is disabled, the instruction TABRDC [m] reads the ROM data as defined by TBLP and the current program counter bits.
Rev. 1.00
9
December 15, 2009
HT82K74E/HT82K74EE
Table Location Bits Instruction b10 TABRDC[m] TABRDL[m] PC10 1 b9 PC9 1 b8 PC8 1 b7 @7 @7 b6 @6 @6 b5 @5 @5 b4 @4 @4 b3 @3 @3 b2 @2 @2 b1 @1 @1 b0 @0 @0
Table Location Note: PC10~PC8: Current program counter bits when TBHP is disabled TBHP register bit2~bit0 when TBHP is enabled @7~@0: Table Pointer TBLP bits
Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the last page which is stored there using the ORG statement. The value at this ORG statement is 700H which refers to the start address of the last page within the 2K Program Memory of device. The table pointer is setup here to have an initial value of 06H. This will ensure that the first data read from the data ta-
ble will be at the Program Memory address 706H or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the TABRDC [m] instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the TABRDL [m] instruction is executed.
P ro g ra m C o u n te r H ig h B y te TBLP
P ro g ra m M e m o ry
TBHP TBLP
P ro g ra m M e m o ry
TBLH T a b le C o n te n ts H ig h B y te
S p e c ifie d b y [m ] T a b le C o n te n ts L o w B y te
TBLH H ig h B y te o f T a b le C o n te n ts
S p e c ifie d b y [m ] Low B y te o f T a b le C o n te n ts
Table Read - TBLP only
Table Read - TBLP/TBHP
Rev. 1.00
10
December 15, 2009
HT82K74E/HT82K74EE
tempreg1 tempreg2 db db : : a,06h tblp,a : : tempreg1 ? ? ; temporary register #1 ; temporary register #2
mov mov
; initialise table pointer - note that this address ; is referenced ; to the last page or present page
tabrdl
; ; ; ;
transfers value in table referenced by table pointer to tempregl data at prog. memory address 706H transferred to tempreg1 and TBLH
dec tabrdl
tblp tempreg2
; reduce value of table pointer by one ; ; ; ; ; ; ; ; transfers value in table referenced by table pointer to tempreg2 data at prog.memory address 705H transferred to tempreg2 and TBLH in this example the data 1AH is transferred to tempreg1 and data 0FH to register tempreg2 the value 00H will be transferred to the high byte register TBLH
: : org dc 700h ; sets initial address of last page
00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : :
Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use the table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation.
Rev. 1.00
11
December 15, 2009
HT82K74E/HT82K74EE
Data Memory
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into two sections, the first of these is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control. Structure The two sections of Data Memory, the Special Purpose and General Purpose Data Memory are located at consecutive locations. All are implemented in RAM and are 8-bit wide. The start address of the Data Memory for all devices is the address 00H. Registers which are common to all microcontrollers, such as ACC, PCL, etc., have the same Data Memory address.
00H S p e c ia l P u r p o s e D a ta M e m o ry 3FH 40H G e n e ra l P u rp o s e D a ta M e m o ry 9FH
Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant Special Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the value 00H.
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H PA PAC PB PBC PC PCC PD PDC PE PEC W SR CTLR TBHP OSCC RFCTR G e n e ra l P u rp o s e D a ta M e m o ry (9 6 B y te s ) :U nused, re a d a s "0 0 " ACC PCL TBLP TBLH W DTS STATUS IN T C TM RH TM RL TM RC PTR S p e c ia l P u r p o s e D a ta M e m o ry IA R MP
Data Memory Structure Note: Most of the Data Memory bits can be directly manipulated using the SET [m].i and CLR [m].i with the exception of a few dedicated bits. The Data Memory can also be accessed through the memory pointer register, MP.
1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 40H
General Purpose Data Memory All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user program for both read and write operations. By using the SET [m].i and CLR [m].i instructions, individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory.
9FH
Special Purpose Data Memory Structure
Rev. 1.00
12
December 15, 2009
HT82K74E/HT82K74EE
Special Function Registers
To ensure successful operation of the microcontroller, certain internal registers are implemented in the Data Memory area. These registers ensure correct operation of internal functions such as timers, interrupts, etc., as well as external functions such as I/O data control. The location of these registers within the Data Memory begins at the address 00H. Any unused Data Memory locations between these special function registers and the point where the General Purpose Memory begins is reserved and attempting to read data from these locations will return a value of 00H. Indirect Addressing Registers - IAR The IAR register, located at Data Memory address 00H, is not physically implemented. This special register allows what is known as indirect addressing, which permits data manipulation using a Memory Pointer indata .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov mov mov mov loop: clr inc sdz jmp continue: The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses. IAR mp block loop ; clear the data at address defined by MP ; increment memory pointer ; check if last memory location has been cleared a,04h ; setup size of block block,a a,offset adres1; Accumulator loaded with first RAM address mp,a ; setup memory pointer with first RAM address stead of the usual direct memory addressing method where the actual memory address is defined. Any actions on the IAR register will result in corresponding read/write operations to the memory location specified by the Memory Pointer MP. Reading the IAR register indirectly will return a result of 00H and writing to the register indirectly will result in no operation. Memory Pointer - MP One Memory Pointer, known as MP, is physically implemented in the Data Memory. The Memory Pointer can be written to and manipulated in the same way as normal registers providing an easy way of addressing and tracking data. When using any operation on the indirect addressing register IAR, it is actually the address specified by the Memory Pointer that the microcontroller will be directed to.
Rev. 1.00
13
December 15, 2009
HT82K74E/HT82K74EE
Accumulator - ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register - PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers - TBLP, TBLH, TBHP These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP is the table pointer and indicates the location where the table data is located. Its value must be setup before any table read commands are executed. Its value can be changed, for example using the INC or DEC instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Once TBHP is enabled, the instruction TABRDC [m] reads the ROM data as defined by TBLP and TBHP value.
b7 TO PDF OV Z AC
Otherwise, the TBHP function selected via a configuration option is disabled, the instruction TABRDC [m] reads the ROM data as defined by TBLP and the current program counter bits. Status Register - STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the CLR WDT or HALT instruction. The PDF flag is affected only by executing the HALT or CLR WDT instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations.
* C is set if an operation results in a carry during an ad-
dition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.
* AC is set if an operation results in a carry out of the
low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.
* Z is set if the result of an arithmetic or logical operation
is zero; otherwise Z is cleared.
* OV is set if an operation results in a carry into the high-
est-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
* PDF is cleared by a system power-up or executing the
CLR WDT instruction. PDF is set by executing the HALT instruction.
* TO is cleared by a system power-up or executing the
CLR WDT or HALT instruction. TO is set by a WDT time-out.
b0 C
S T A T U S R e g is te r
ith m e r r y fla x ilia r y r o fla g O v e r flo w g Ar Ca Au Ze tic /L o g ic O p e r a tio n F la g s c a r r y fla g fla g an n tim e a g e m e n t F la g s fla g e - o u t fla g n te d , re a d a s "0 "
S y s te m M Pow erdow W a tc h d o g N o t im p le m
Status Register Rev. 1.00 14 December 15, 2009
HT82K74E/HT82K74EE
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the interrupt routine can change the status register, precautions must be taken to correctly save it. Interrupt Control Registers - INTC The microcontroller provides an internal timer/event counter overflow interrupt. By setting various bits within this register using standard bit manipulation instructions, the enable/disable function of each interrupt can be independently controlled. A master interrupt bit within this register, the EMI bit, acts like a global enable/disable and is used to set all of the interrupt enable bits on or off. This bit is cleared when an interrupt routine is entered to disable further interrupt and is set by executing the RETI instruction. Timer/Event Counter Registers TMRH, TMRL, TMRC All devices possess a single internal 16-bit count-up timer. An associated register pair known as TMRL/TMRH is the location where the timer 16-bit value is located. This register can also be preloaded with fixed data to allow different time intervals to be setup. An associated control register, known as TMRC, contains the setup information for this timer, which determines in what mode the timer is to be used as well as containing the timer on/off control function. Watchdog Timer Register - WDTS The Watchdog function in the microcontroller provides an automatic reset function giving the microcontroller a means of protection against spurious jumps to incorrect Program Memory addresses. To implement this, a timer is provided within the microcontroller which will issue a reset command when its value overflows.To provide variable Watchdog Timer reset times, the Watchdog Timer clock source can be divided by various division ratios, the value of which is set using the WDTS register. By writing directly to this register, the appropriate division ratio for the Watchdog Timer clock source can be setup. Note that only the lower 3 bits are used to set division ratios between 1 and 128. Input/Output Ports and Control Registers Within the area of Special Function Registers, the I/O registers and their associated control registers play a prominent role. All I/O ports have a designated register correspondingly labeled as PA, PB, PC, PD and PE. These labeled I/O registers are mapped to specific addresses within the Data Memory as shown in the Data Memory table, which are used to transfer the appropriate output or input data on that port. With each I/O port
there is an associated control register labeled PAC, PBC, PCC, PDC, PEC also mapped to specific addresses with the Data Memory. The control register specifies which pins of that port are set as inputs and which are set as outputs. To setup a pin as an input, the corresponding bit of the control register must be set high, for an output it must be set low. During program , it is important to first setup the control registers to specify which pins are outputs and which are inputs before reading data from or writing data to the I/O ports. One flexible feature of these registers is the ability to directly program single bits using the SET [m].i and CLR [m].i instructions. The ability to change I/O pins from output to input and vice versa by manipulating specific bits of the I/O control registers during normal program operation is a useful feature of these devices.
EEPROM Data Memory
An area of EEPROM, which stands for Electrically Erasable Programmable Read Only Memory, is contained within the device. This type of memory is non-volatile with data retention even after power is removed. This type of memory is useful for storing information such as product identification numbers, calibration values, user data, system setup data etc. EEPROM Memory Structure The EEPROM has a capacity is 128 organised into a structure of 8-bit words. The EEPROM is an IIC type device and therefore operates using a two wire serial bus. Accessing the EEPROM Data Memory The two IIC lines are the Serial Clock line, SCL, and the Serial Data line SDA. The SDA pin is shared with I/O pin PE0, while the SCL pin is connected to internal I/O PE1. Normal I/O control software instructions for PE0 and PE1 are used to control read and write operations on the EEPROM.
* Serial data - SDA
The SDA line is the bidirectional EEPROM serial data line which is shared with pin PE0. If it is transfer data must be output mode, and it receive data should be set input mode and select pull high resistor by option.
* Serial data - SCL
The SCL line is the EEPROM serial clock input line which is shared with internal I/O PE1. The SCL input clocks data into the EEROM on its positive edge and clocks data out of the EEPROM on its negative edge.
* Clock and data transition
Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a START or STOP condition.
Rev. 1.00
15
December 15, 2009
HT82K74E/HT82K74EE
* Start condition
Write Operations
* Byte write
A high-to-low transition of SDA with SCL high will be interpreted as a start condition which must precede any other command - refer to the Start and Stop Definition Timing diagram.
* Stop condition
A low-to-high transition of SDA with SCL high will be interpreted as a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode - refer to Start and Stop Definition Timing Diagram.
* Acknowledge
All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle.
D a ta a llo w e d to c h a n g e SDA
A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. After receiving the 8-bit data word, the EEPROM will output a zero and the addressing device, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle to the non-volatile memory. All inputs are disabled during this write cycle and EEPROM will not respond until the write cycle is completed. Refer to Byte write timing diagram.
* Acknowledge polling
To maximise bus throughput, one technique is to allow the master to poll for an acknowledge signal after the start condition and the control byte for a write command have been sent. If the device is still busy implementing its write cycle, then no ACK will be returned. The master can send the next read/write command when the ACK signal has finally been received.
* Read operations
SCL S ta rt c o n d itio n A d d re s s o r a c k n o w le d g e v a lid NoACK s ta te
S to p c o n d itio n
Device Addressing All EEPROM devices require an 8-bit device address word following a start condition to enable the EEPROM for read or write operations. The device address word consist of a mandatory one, zero sequence for the first four most significant bits. Refer to the diagram showing the Device Address. This is common to all the EEPROM devices. The next three bits are all zero bits. The 8th bit of device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. If the comparison of the device address is successful then the EEPROM will output a zero as an ACK bit. If not, the EEPROM will return to a standby state.
1 0 1 0 0 0 0 R /W
The data EEPROM supports three read operations, namely, current address read, random address read and sequential read. During read operation execution, the read/write select bit should be set to 1.
* Current address read
The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the EEPROM power is maintained. The address will roll over during a read from the last byte of the last memory page to the first byte of the first page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller should respond a No ACK - High - signal and a following stop condition - refer to Current read timing.
S e n d W r ite C o m m a n d
D e v ic e A d d r e s s
S e n d S to p C o n d itio n to In itia te W r ite C y c le S e n d S ta rt S e n d C o tr o ll B y te w ith R /W = 0
(A C K = 0 )? Yes N e x t O p e r a tio n
No
Acknowledge Polling Flow
Rev. 1.00
16
December 15, 2009
HT82K74E/HT82K74EE
* Random read * Sequential read
A random read requires a dummy byte write sequence to load in the data word address which is then clocked in and acknowledged by the EEPROM. The microcontroller must then generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller should respond with a No ACK signal - high - followed by a stop condition. Refer to Random read timing.
Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledgment. As long as the EEPROM receives an acknowledgment, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will roll over and the sequential read continues. The sequential read operation is terminated when the microcontroller responds with a No ACK signal - high - followed by a stop condition.
D e v ic e a d d r e s s SDA S S ta rt R /W ACK
W o rd a d d re s s
DATA P ACK ACK S to p
Byte Write Timing
D e v ic e a d d r e s s SDA S S ta rt ACK
DATA
S to p P NoACK
Current Read Timing
D e v ic e a d d r e s s SDA S S ta rt ACK
W o rd a d d re s s S
D e v ic e a d d r e s s
DATA
S to p P NoACK
ACK S ta rt
ACK
Random Read Timing
D e v ic e a d d r e s s SDA S S ta rt ACK
DATA n
DATA n+1
DATA n+x
S to p P NoACK
ACK
Sequential Read Timing
Rev. 1.00
17
December 15, 2009
HT82K74E/HT82K74EE
Data EEPROM Timing Diagrams
tf SCL tS
U
tr tL
OW D
tH
IG H
:S
TA
tH tS
P
:S
TA
tH
D
:D
AT
tS
U
:D
AT
tS
U
:S
TO
SDA SDA OUT
tA
A
tB V a lid V a lid
UF
SCL SDA 8 th b it W o rd n S to p C o n d itio n
ACK tW
R
S ta rt C o n d itio n
Note:
The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the valid start condition of sequential command.
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high options for all ports and Wake-up option for all I/O pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The device provides 36-bit bidirectional input/output lines labeled with port names PA, PB, PC, PD and PE. These I/O ports are mapped to the Data Memory with addresses as shown in the Special Purpose Data Memory table. All of these I/O lines can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction MOV A,[m], where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. The pull-high resistors are selectable via configuration options and are implemented using weak PMOS transistors. Port Pin Wake-up If the HALT instruction is executed, the device will enter the Power Down Mode, where the system clock will stop Rev. 1.00 18 resulting in power being conserved, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port pins from high to low or low to high. After a HALT instruction forces the microcontroller into the Power Down Mode, the processor will remain in a low-power state until the logic condition of the selected wake-up pin on the port pin changes from high to low or low to high. This function is especially suitable for applications that can be woken up via external switches. Each pin on PA (by bit), PB, PC, PD, PE has the capability to wake-up (by nibble) the device by falling and rising edges. It means once there are one pin in is low or high the I/O cannot wake-up the MCU. I/O Port Control Registers Each I/O port has its own control register PAC, PBC, PCC, PDC and PEC to control the input/output configuration. With this control register, each CMOS output or input with or without pull-high resistor structures can be reconfigured dynamically under software control. Each of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a 1. This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a 0, the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the
December 15, 2009
HT82K74E/HT82K74EE
V C o n tr o l B it Q D CK S Q P u ll- H ig h O p tio n
DD
D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
W eak P u ll- u p
I/O D a ta B it Q D CK S Q
P o rt
W r ite D a ta R e g is te r P A O u tp u t C o n fig u r a tio n
M U
P u ll- L o w X W a k e - u p o p tio n fo r a n y I/O p o rt
R e a d D a ta R e g is te r W a k e -u p fo r a n y I/O p o rt P A 2 /T M R
Input/Output Ports output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. Pin-shared Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. The chosen function of the multi-function I/O pins is set by application program control.
* External Timer Clock Input
PD3 has falling and rising edge wake-up function if its wake-up function is enabled by related configuration option. In halt mode if PD2 wakes up the MCU, the bit6 named ZA_wakeup in the Wake-up Status Register WSR will be set. Similarly, if PD3 wakes up the MCU, the bit7 named ZB_wake-up in the Wake-up Status Register WSR will be set. If the bit ZA_wake-up or ZB_wakeup is read by application program, the bit will be cleared. I/O Pin Structures The diagrams illustrate the I/O pin internal structures. As the exact logical construction of the I/O pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, all of the data and port control register will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. If the PAC, PBC, PCC, PDC and PEC port control registers are programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated PA, PB, PC, PD and PE port data registers are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading
T1 S y s te m C lo c k T2 T3 T4 T1 T2 T3 T4
The external timer pin TMR is pin-shared with the I/O pin PA2. To configure this pin to operate as timer input, the corresponding control bits in the timer control register must be correctly set. For applications that do not require an external timer input, this pin can be used as a normal I/O pin. Note that if used as a normal I/O pin the timer mode control bits in the timer control register must select the timer mode, which has an internal clock source, to prevent the input pin from interfering with the timer operation.
* The VA/VB is for V-axis Function
The VA/VB pins are shared with the pins PD0/PD1. PD0 or PD1 have falling and rising edge wake-up functions if their wake-up function is enabled by the related configuration option. In the Power-down mode, if PD0 wakes up the MCU, the bit3 named VA_wake-up in the Wake-up Status Register WSR will be set. Similarly, if PD1 wakes up the MCU, bit4 named VB_wakeup in the Wake-up Status Register WSR will be set. If the bit VA_wake-up or VB_wakeup is read by application program, the bit will be cleared.
* The ZA/ZB is for Z-axis function
P o rt D a ta
The ZA/ZB pins are shared with the PD2/PD3, PD2 or
W r ite to P o r t
R e a d fro m
P o rt
Read/Write Timing
Rev. 1.00
19
December 15, 2009
HT82K74E/HT82K74EE
the correct value into the port control register or by programming individual bits in the port control register using the SET [m].i and CLR [m].i instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. All I/O ports have the capability of providing wake-up functions. When the device is in the Power Down Mode, various methods are available to wake the device up. One of these is a transition of any of the selected wake-up pins. An external clock source is used when the timer is in the event counting mode, the clock source being provided on shared pin PA2/TMR. Depending upon the condition of the TE bit, each high to low, or low to high transition on the PA2/TMR pin will increment the counter by one. Timer Registers - TMRH, TMRL The TMRH and TMRL registers are two 8-bit special function register locations within the special purpose Data Memory where the actual timer value is stored. The value in the timer counter increases by one each time an internal clock pulse is received or an external transition occurs on the PA2/TMR pin. The timer will count from the initial value loaded by the preload register to the full count value of FFFFH at which point the timer overflows and an internal interrupt signal generated. The timer value will then be reset with the initial preload register value and continue counting. For a maximum full range count of 0000H to FFFFH the preload registers must first be cleared to 0000H. It should be noted that after power-on the preload registers will be in an unknown condition. Note that if the Timer/Event Counter is not running and data is written to its preload registers, this data will be immediately written into the actual counter. However, if the counter is enabled and counting, any new data written into the preload registers during this period will remain in the preload registers and will only be written into the actual counter the next time an overflow occurs. Accessing these registers is carried out in a specific way. It must be noted that when using instructions to preload data into the low byte register, namely TMRL, the data will only be placed in a low byte buffer and not directly into the low byte register. The actual transfer of the data into the low byte register is only carried out when a write to its associated high byte register, namely TMRH, is executed. On the other hand, using instructions to preload data into the high byte timer register will result in the data being directly written to the high byte register. At the same time the data in the low byte buffer will be transferred into its associated low byte register. For this reason, when preloading data into the 16-bit timer registers, the low byte should be written first. It
Timer/Event Counters
The provision of timers form an important part of any microcontroller giving the designer a means of carrying out time related functions. The device contains an internal 16-bit count-up timer which has three operating modes. The timer can be configured to operate as a general timer, external event counter or as a pulse width measurement device. There are three registers related to the Timer/Event Counter, TMRL, TMRH and TMRC. The TMRL/TMRH register pair are the registers that contains the actual timing value. Writing to this register pair places an initial starting value in the Timer/Event Counter preload register while reading retrieves the contents of the Timer/Event Counter. The TMRC register is a Timer/Event Counter control register, which defines the timer options, and determines how the timer is to be used. The timer clock source can be configured to come from the internal system clock divided by 4 or from an external clock on shared pin PA2/TMR. Configuring the Timer/Event Counter Input Clock Source The timer clock source can originate from either the system clock divided by 4 or from an external clock source. The system clock divided by 4 is used when the timer is in the timer mode or in the pulse width measurement mode.
D a ta B u s L o w B y te B u ffe r 1 6 - B it P r e lo a d R e g is te r R e lo a d
TM 1 TM R TE fS
YS
TM 0
/4
T im e r /E v e n t C o u n te r M o d e C o n tro l TON
H ig h B y te
L o w B y te
O v e r flo w to In te r r u p t
1 6 - B it T im e r /E v e n t C o u n te r
16-bit Timer/Event Counter Structure
Rev. 1.00
20
December 15, 2009
HT82K74E/HT82K74EE
must also be noted that to read the contents of the low byte register, a read to the high byte register must first be executed to latch the contents of the low byte buffer from its associated low byte register. After this has been done, the low byte register can be read in the normal way. Note that reading the low byte timer register directly will only result in reading the previously latched contents of the low byte buffer and not the actual contents of the low byte timer register. Timer Control Register - TMRC The flexible features of the Holtek microcontroller Timer/Event Counters enable them to operate in three different modes, the options of which are determined by the contents of the Timer Control Register TMRC. Together with the TMRL and TMRH registers, these three registers control the full operation of the Timer/Event Counter. Before the timer can be used, it is essential that the TMRC register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialisation. To choose which of the three modes the timer is to operate in, the timer mode, the event counting mode or the pulse width measurement mode, bits TM0 and TM1 must be set to the required logic levels. The timer-on bit TON or bit 4 of the TMRC register provides the basic on/off control of the timer, setting the bit high allows the counter to run, clearing the bit stops the counter. If the timer is in the event count or pulse width measurement mode the active transition edge level type is selected by the logic level of the TE or bit 3 of the TMRC register. Configuring the Timer Mode In this mode, the timer can be utilised to measure fixed time intervals, providing an internal interrupt signal each time the counter overflows. To operate in this mode, bits TM1 and TM0 of the TMRC register must be set to 1 and 0 respectively. In this mode, the internal clock is used as the timer clock. The timer-on bit, TON, must be set high to enable the timer to run. Each time an internal clock high to low transition occurs, the timer increments by one. When the timer is full and overflows, the timer will be reset to the value already loaded into the preload register and continue counting. If the timer interrupt is enabled, an interrupt signal will also be generated. The timer interrupt can be disabled by ensuring that the ETI bit in the INTC register is cleared to zero. Note: The timer overflow cant wake-up the MCU from Power Down Mode.
b7 TM 1
b0 TM 0 TON TE T im e r /E v e n t C o u n te r C o n tr o l R e g is te r N o t im p le m e n te d , r e a d a s " 0 " T o d e fin e th e a c tiv e e d g e o f T M R 1 : a c tiv e o n h ig h to lo w 0 : a c tiv e o n lo w to h ig h T o e n a b le o r d is a b le tim e r c o u n tin g 1 : e n a b le 0 : d is a b le N o t im p le m e n te d , r e a d a s " 0 " O p e r a tin g m o d e TM 0 TM 1 no 0 0 ev 1 0 tim 0 1 1 1 pu s e le c t m od entc erm ls e w e ava o u n te ode ( id th m ila b rm in te ea le o d e ( e x te r n a l c lo c k ) r n a l c lo c k ) s u re m e n t m o d e p in in p u t s ig n a l
Timer/Event Counter Control Register
fS
YS
/4
In c re m e n t T im e r C o u n te r
T im e r + 1
T im e r + 2
T im e r + N
T im e r + N
+1
Timer Mode Timing Chart
Rev. 1.00
21
December 15, 2009
HT82K74E/HT82K74EE
Configuring the Event Counter Mode In this mode, a number of externally changing logic events, occurring on external pin PA2/TMR, can be recorded by the internal timer. For the timer to operate in the event counting mode, bits TM1 and TM0 of the TMRC register must be set to 0 and 1 respectively. The timer-on bit, TON must be set high to enable the timer to count. With TE low, the counter will increment each time the PA2/TMR pin receives a low to high transition. If the TE bit is high, the counter will increment each time PA2/TMR receives a high to low transition. As in the case of the other two modes, when the counter is full and overflows, the timer will be reset to the value already loaded into the preload register and continue counting. If the timer interrupt is enabled, an interrupt signal will also be generated. The timer interrupt can be disabled by ensuring that the ETI bit in the INTC register is cleared to zero. To ensure that the external pin PA2/TMR is configured to operate as an event counter input pin, two things have to happen. The first is to ensure that the TM0 and TM1 bits place the timer/event counter in the event counting mode, the second is to ensure that the port control register configures the pin as an input. In the Event Counting mode, the Timer/Event Counter will continue to record externally changing logic events on the timer input pin, even if the microcontroller is in the Power Down Mode. Configuring the Pulse Width Measurement Mode In this mode, the width of external pulses applied to the pin-shared external pin PA2/TMR can be measured. In the Pulse Width Measurement Mode, the timer clock source is supplied by the internal clock. For the timer to operate in this mode, bits TM0 and TM1 must both be set high. If the TE bit is low, once a high to low transition has been received on the PA2/TMR pin, the timer will start counting until the PA2/TMR pin returns to its original high level. At this point the TON bit will be automatically reset to zero and the timer will stop counting. If the TE bit is high, the timer will begin counting once a low to high transition has been received on the PA2/TMR pin and stop counting when the PA2/TMR pin returns to its original low level. As before, the TON bit will be automatically reset to zero and the timer will stop counting. It is important to note that in the Pulse Width Measurement Mode, the TON bit is automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the TON bit can only be reset to zero under program control. The residual value in the timer, which can now be read by the program, therefore represents the length of the pulse received on pin PA2/TMR. As the TON bit has now been reset any further transitions on the PA2/TMR pin will be ignored. Not until the TON bit is again set high by the program can the timer begin further pulse width measurements. In this way single shot pulse measurements can be easily made. It should be noted that in this mode the counter is controlled by logical transitions on the PA2/TMR pin and not by the logic level. As in the case of the other two modes, when the counter is full and overflows, the timer will be reset to the value already loaded into the preload register. If the timer interrupt is enabled, an interrupt signal will also be generated. To ensure that the external pin PA2/TMR is configured to operate as a pulse width measuring input pin, two things have to happen. The first is to ensure that the TM0 and TM1 bits place the timer/event counter in the pulse width measuring mode, the second is to ensure that the port control register configures the pin as an input.
E x te rn a l E v e n t In c re m e n t T im e r C o u n te r
T im e r + 1
T im e r + 2
T im e r + 3
Event Counter Mode Timing Chart
E x te r n a l T im e r P in In p u t T0O N orT1O N ( w ith T 0 E o r T 1 E = 0 ) fS
YS
/4 T im e r F s y s /4 +1 +2 +3 +4
In c re m e n t T im e r C o u n te r
is s a m p le d a t e v e r y fa llin g e d g e o f T 1 .
Pulse Width Measure Mode Timing Chart Rev. 1.00 22 December 15, 2009
HT82K74E/HT82K74EE
I/O Interfacing The Timer/Event Counter, when configured to run in the event counter or pulse width measurement mode, require the use of the external PA2 pin for correct operation. As this pin is a shared pin it must be configured correctly to ensure it is setup for use as a Timer/Event Counter input and not as a normal I/O pin. This is implemented by ensuring that the mode select bits in the Timer/Event Counter control register, select either the event counter or pulse width measurement mode. Additionally the Port Control Register PAC bit 2 must be set high to ensure that the pin is setup as an input. Any pull-high resistor configuration option on this pin will remain valid even if the pin is used as a Timer/Event Counter input. Programming Considerations When configured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronised with the overall operation of the microcontroller. In this mode when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respective internal interrupt vector. For the pulse width measurement mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. As this is an external event and not sync h ro n is ed w i t h t h e i n t e r nal t i m e r c l o ck, t h e microcontroller will only see this external event when the next timer clock pulse arrives. As a result, there may be small differences in measured values requiring programmers to take this into account during programming. The same applies if the timer is configured to be in the event counting mode, which again is an external event and not synchronised with the internal system or timer clock. When the Timer/Event Counter is read, or if data is written to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. Care must be taken to ensure that the timers are properly initialised before using them for the first time. The associated timer interrupt enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. The edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. It is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer registers are unknown. After the timer has been initialised the timer can be turned on and off by controlling the enable bit in the timer control register. Note that setting the timer enable bit high to turn the timer on, should only be executed after the timer mode bits have been properly setup. Setting the timer enable bit high together with a mode bit modification, may lead to improper timer operation if executed as a single timer control register byte write instruction. When the Timer/Event counter overflows, its corresponding interrupt request flag in the interrupt control register will be set. If the timer interrupt is enabled this will in turn generate an interrupt signal. But the timer overflow cant wake-up the MCU if MCU is in a Power down condition.
Rev. 1.00
23
December 15, 2009
HT82K74E/HT82K74EE
Timer Program Example This program example shows how the Timer/Event Counter registers are setup, along with how the interrupts are enabled and managed. Note how the Timer/Event Counter is turned on, by setting bit 4 of the Timer Control Register. The Timer/Event Counter can be turned off in a similar way by clearing the same bit. This example program sets the Timer/Event Counter to be in the timer mode, which uses the internal system clock as the clock source. org 04h reti org 008h ; Timer/Event Counter interrupt vector jmp tmrint ; jump here when Timer overflows : org 20h ; main program ;internal Timer/Event Counter interrupt routine tmrint: : ; Timer/Event Counter main program placed here : reti : : begin: ;setup Timer registers mov a,09bh ; setup Timer low register mov tmrl,a; ; load low register first mov a, 0aah ; setup timer high register mov tmrh,a mov a,080h ; setup Timer control register mov tmrc,a ; timer mode is used ; setup interrupt register mov a,005h ; enable master interrupt and timer interrupt mov intc,a set tmrc.4 ; start Timer/Event Counter - note mode bits must be previously setup
Interrupts
Interrupts are an important part of any microcontroller system. When an internal function such as a Timer/Event Counter overflow, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. This device contains a single internal Timer/Event counter interrupt. Interrupt Register Overall interrupt control, which means interrupt enabling and request flag setting, is controlled by a single interrupt control register, which is located in the Data Memory. By controlling the appropriate enable bits in this register the interrupt can be enabled or disabled. Also when an interrupt occurs, the request flag will be set by the microcontroller. The global enable flag if cleared to zero will disable all interrupts. Interrupt Operation A Timer/Event Counter overflow, will generate an interrupt request by setting its corresponding request flag, if its interrupt enable bit is set. When this happens, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the correspondRev. 1.00 24 ing interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a JMP statement which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a RETI statement, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. Once an interrupt subroutine is serviced, other interrupts will be blocked, as the EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full.
December 15, 2009
HT82K74E/HT82K74EE
Timer/Event Counter Interrupt For a Timer/Event Counter interrupt to occur, the global interrupt enable bit, EMI, and its corresponding timer interrupt enable bit, ETI, must first be set. An actual Timer/Event Counter interrupt will take place when the Timer/Event Counter request flag, TF, is set, a situation that will occur when the Timer/Event Counter overflows. When the interrupt is enabled, the stack is not full and a Timer/Event Counter overflow occurs, a subroutine call to the timer interrupt vector at location 08H, will take place. When the interrupt is serviced, the timer interrupt request flag, TF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Programming Considerations By disabling the interrupt enable bit, the requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this
b7 TF ETI b0 EMI IN T C R e g is te r M a s te r In te r r u p t G lo b a l E n a b le 1 : g lo b a l e n a b le 0 : g lo b a l d is a b le N o im p le m e n te d , r e a d a s " 0 " T im e r /E v e n t C o u n te r In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le N o im p le m e n te d , r e a d a s " 0 " N o im p le m e n te d , r e a d a s " 0 "
condition in the interrupt control register until the corresponding interrupt is serviced or until the request flag is cleared by a software instruction. It is recommended that programs do not use the CALL subroutine instruction within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. All of these interrupts have the capability of waking up the processor when in the Power Down Mode. Only the Program Counter is pushed onto the stack. If the contents of the accumulator or status register are altered by the interrupt service program, which may corrupt the desired control sequence, then the contents should be saved in advance.
T im e r /E v e n t C o u n te r In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e N o im p le m e n te d , r e a d a s " 0 "
Interrupt Control Register
Rev. 1.00
25
December 15, 2009
HT82K74E/HT82K74EE
Reset and Initialisation
A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. One example of this is where after power has been applied and the microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are five ways in which a microcontroller reset can occur, through events occurring both internally and externally:
* Power-on Reset
10kW
inhibited. After the RES line reaches a certain voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the microcontroller will begin normal operation. The abbreviation SST in the figures stands for System Start-up Timer.
VDD RES S S T T im e - o u t In te rn a l R e s e t 0 .9 V tR
DD
STD
Power-On Reset Timing Chart For most applications a resistor connected between VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES pin should be kept as short as possible to minimise any stray noise interference.
VDD 100kW RES 0 .1 m F VSS
Basic Reset Circuit For applications that operate within an environment where more noise is present the Enhanced Reset Circuit shown is recommended.
0 .0 1 m F 100kW RES VDD
0 .1 m F VSS
The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. Although the microcontroller has an internal RC reset function, if the VDD power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. For this reason it is recommended that an external RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin remains low for an extended period to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be
Enhanced Reset Circuit More information regarding external reset circuits is located in Application Note HA0075E on the Holtek website.
* RES Pin Reset
This type of reset occurs when the microcontroller is already running and the RES pin is forcefully pulled low by external hardware such as an external switch. In this case as in the case of other reset, the Program Counter will reset to zero and program execution initiated from this point.
RES S S T T im e - o u t In te rn a l R e s e t 0 .4 V 0 .9 V
DD DD
tR
STD
RES Reset Timing Chart Rev. 1.00 26 December 15, 2009
HT82K74E/HT82K74EE
* Low Voltage Reset - LVR
Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the Power Down function or Watchdog Timer. The reset flags are shown in the table: TO PDF 0 u 1 1 0 u u 1 RESET Conditions RES reset during power-on RES or LVR reset during normal operation WDT time-out reset during normal operation WDT time-out reset during Power Down
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The LVR function is selected via a configuration option. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for a time greater than that specified by tLVR in the A.C. characteristics. If the low supply voltage state does not exceed this value, the LVR will ignore the low supply voltage and will not perform a reset function. The actual VLVR value can be selected via configuration options.
LVR tR S S T T im e - o u t In te rn a l R e s e t
STD
Note: u stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Condition After RESET Reset to zero All interrupts will be disabled Clear after reset, WDT begins counting Timer Counter will be turned off
Low Voltage Reset Timing Chart
* Watchdog Time-out Reset during Normal Operation
Program Counter Interrupts WDT Timer/Event Counter
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except that the Watchdog time-out flag TO will be set to 1.
W D T T im e - o u t
tR
S S T T im e - o u t In te rn a l R e s e t
STD
Input/Output Ports I/O ports will be setup as inputs Stack Pointer Stack Pointer will point to the top of the stack
WDT Time-out Reset during Normal Operation Timing Chart
* Watchdog Time-out Reset during Power Down
The Watchdog time-out Reset during Power Down is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to 0 and the TO flag will be set to 1. Refer to the A.C. Characteristics for tSST details.
W D T T im e - o u t
tS
S S T T im e - o u t
ST
WDT Time-out Reset during Power Down Timing Chart
Rev. 1.00
27
December 15, 2009
HT82K74E/HT82K74EE
The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Register PCL MP ACC TBLP TBLH STATUS INTC TMRL TMRH TMRC PA PAC PB PBC PC PCC PD PDC PE PEC WSR CTLR OSCC RFCTR PTR TBHP Note: Reset (Power-on) 000H xxxx xxxx xxxx xxxx xxxx xxxx -xxx xxxx --00 xxxx --0- -0-0 xxxx xxxx xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 ---- 1111 xxxx x--0000 0x00 0000 0000 0000 0000 0000 0000 0000 0000 * means warm reset - not implemented u means unchanged x means unknown WDT time-out RES Reset (Normal Operation) (Normal Operation) 000H uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --1u uuuu --0- -0-0 xxxx xxxx xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 ---- 1111 xxxx x--0000 0x00 0000 0000 0000 0000 0000 0000 0000 0uuu 000H uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --00 uuuu --0- -0-0 xxxx xxxx xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 ---- 1111 xxxx x--0000 0x00 0000 0000 0000 0000 0000 0000 0000 uuuu RES Reset (HALT) 000H uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --00 uuuu --0- -0-0 xxxx xxxx xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 ---- 1111 xxxx x--0000 0x00 0000 0000 0000 0000 0000 0000 0000 0uuu WDT Time-out (HALT)* 000H uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --11 uuuu --u- -u-u uuuu uuuu uuuu uuuu uu-u u--uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- uuuu ---- uuuu uuuu u--uuuu uxuu uuu0 uuuu 000u uuuu uuuu uuuu 0000 0uuu
Rev. 1.00
28
December 15, 2009
HT82K74E/HT82K74EE
Oscillator
There are two oscillator circuits contained within the device. The first is the system oscillator which utilises an external crystal and the second is the Watchdog timer oscillator which is fully integrated and requires no external components. System Clock Configurations There is one oscillator mode Crystal. For Crystal mode no built-in capacitor between OSC1, OSC2 and GND. The simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation, without requiring external capacitors. However, for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, C1 and C2. Using a ceramic resonator will usually require two small value capacitors, C1 and C2, to be connected as shown for oscillation to occur. The values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer's specification. In most applications, resistor R1 is not required, however for those applications where the LVR function is not used, R1 may be necessary to ensure the oscillator stops running when VDD falls below its operating range. More information regarding the oscillator is located in Application Note HA0075E on the Holtek website.
C1
an extremely low standby current level. This occurs because when the device enters the Power Down Mode, the system oscillator is stopped which reduces the power consumption to extremely low levels, however, as the device maintains its present internal condition, it can be woken up at a later stage and continue running, without requiring a full reset. This feature is extremely important in application areas where the microcontroller must have its power supply constantly maintained to keep the device in a known condition but where the power supply capacity is limited such as in battery applications. Entering the Power Down Mode There is only one way for the device to enter the Power Down Mode and that is to execute the HALT instruction in the application program. When this instruction is executed, the following will occur:
* The system oscillator will stop running and the appli-
cation program will stop at the HALT instruction.
* The Data Memory contents and registers will maintain
their present condition.
* The WDT will be cleared and resume counting if the
WDT is enabled and the clock source is selected to come from the WDT oscillator.
* The I/O ports will maintain their present condition. * In the status register, the Power Down flag, will be set
OSC1
R1
and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the Power Down Mode is to keep the current consumption of the microcontroller to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. If the configuration option has enabled the Watchdog Timer internal oscillator, then this will continue to run when in the Power Down Mode and will thus consume some power.
OSC2
C2
Crystal/Ceramic Oscillator Watchdog Timer Oscillator The WDT oscillator is a fully self-contained free running on-chip RC oscillator with a typical period of 71ms at 3V requiring no external components. When the device enters the Power Down Mode, the system clock will stop running but the WDT oscillator continues to free-run and to keep the watchdog active. However, to preserve power in certain applications the WDT oscillator can be disabled via a configuration option.
Power Down Mode and Wake-up
Power Down Mode All of the Holtek microcontrollers have the ability to enter a Power Down Mode. When the device enters this mode, the normal operating current, will be reduced to
Rev. 1.00
29
December 15, 2009
HT82K74E/HT82K74EE
Wake-up After the system enters the Power Down Mode, it can be woken up from one of various sources listed as follows:
* An external reset * An external falling or rising edge on any of the I/O pins * A system interrupt * A WDT overflow (if the contents of the PTR are zeros) * A PTR overflow occurs (if the contents of the PTR are
Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. It operates by providing a device reset when the WDT counter overflows. The WDT clock is supplied by its own internal dedicated internal WDT oscillator. Note that if the WDT configuration option has been disabled, then any instruction relating to its operation will result in no operation. The WDT function is selected by a configuration option. There is also an internal register associated with the WDT named WDTS to select various WDT time-out periods in the device. The clock source of the WDT comes from the internal WDT oscillator and its clock period may vary with VDD, temperature and process variation. The WDT clock is further divided by an internal 6-stage counter followed by a 7-stage prescaler to obtain longer WDT time-out period selected by the WDT prescaler rate selection bits, WS2~WS0, in the associated WDT register known as WDTS. There is only one instruction to clear the Watchdog Timer known as CLR WDT. As the instruction CLR WDT is executed, all contents of the 6-stage counter and 7-stage prescaler will be clear. It makes the WDT time-out period more accurate relatively. Under normal program operation, a WDT time-out will initialise a device reset and set the status bit TO. However, if the system is in the Power Down Mode, when a WDT time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the WDT. The first is an external hardware reset, which means a low level on the RES pin, the second is using the watchdog software instructions and the third is via a HALT instruction. Although the WDT overflow is a source to wake up the MCU from the Power Down Mode, there are some limitations on the conditions at which the WDT overflow occurs. If the WDT function is enabled and the PTR contents are equal to zeros, the WDT overflow will occur to wake up the MCU from the Power Down Mode. If the PTR contents are not equal to zeros, the WDT overflow will not occur in Power Down Mode even if the WDT function has been enabled.
not equal to zeros) If the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the HALT instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Note that the WDT time-out will not occur if the contents of the Period Timer Register (PTR) are not equal to zeros. Each pin on Port A or any nibble on other ports can be setup via configuration options to permit a negative or positive transition on the pin to wake-up the system. When a port pin wake-up occurs, the program will resume execution at the instruction following the HALT instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the HALT instruction. In this situation, the interrupt will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the Power Down Mode, the wake-up function of the related interrupt will be disabled. No matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to 512 system clock periods will be required before normal system operation resumes. However, if the wake-up has originated due to an interrupt, the actual interrupt subroutine execution will be delayed by additional one or more cycles. If the wake-up results in the execution of the next instruction following the HALT instruction, this will be executed immediately after the 512 system clock period delay has ended.
Rev. 1.00
30
December 15, 2009
HT82K74E/HT82K74EE
b7 W S2 W S1 b0 W S0 W D T S R e g is te r W D T p r e s c a le r r a te s e le c W W S0 W S1 W S2 W 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1 1 N otused t :1 :4 :8 :1 6 :3 2 :6 4 :1 2 8 D T R a te D T is d is a b le d
Watchdog Timer Register
CLR
W D T F la g CLR CLR 7 - b it P r e s c a le r 6 - b it C o u n te r
W D T O s c illa to r
8 -to -1 M U X W D T T im e - o u t
W S0~W S2
Watchdog Timer Register
Bit No. 0~2 3 4 5 6 7
MCU Name PF0~PF2 PF3 PF4 PF5 PF6 PF7
Fun. Name Reserved bit VA_wakeup VB_wakeup CNT_WK ZA_wakeup ZB_wakeup
R/W 3/4 R R R R R Always read 0
Description for mouse mode
1: VA change before VB 0: default 1: VB change before VA 0: default 1: MCU wake-up by period counter overflow 0: MCU Wake-up not by period counter 1: ZA change before ZB 0: default 1: ZB change before ZA 0: default
Wakeup Status Register - WSR
Rev. 1.00
31
December 15, 2009
HT82K74E/HT82K74EE
Bit No. MCU Name PFC0 Function Name AMP_ctrl R/W Description for Mouse Mode Control AMP function 1: on AMP function 0: off AMP function (default) This bit is used to decide whether the DC/DC circuit is in operation 0: enable the DC/DC circuit 0: disable the DC/DC circuit Flag for 2.2V/2.0V battery low signal coming from DC/DC block (the battery low level 2.2V or 2.0V is selected by configuration option). 1: battery voltage 2.2V/2.0V 0: battery voltage > 2.2V/2.0V 1.8V Battery Low signal for DC/DC 1.8V Always Off in Power Down Mode. 1: battery voltage 1.8V 0: battery voltage > 1.8V Always read 0
0
R/W
1
PFC1
DC_ctrl
R/W
2
PFC2
LVDF
R
3
PFC3
LVD18
R
4~7
PFC4~7
Reserved bit
R/W
Control Register - CTLR Bit No. 0 1 2 3 4 5 6 7 MCU Name OSC1_C0 OSC1_C1 OSC1_C2 Reserved bit OSC2_C0 OSC2_C1 OSC2_C2 OSC2_C3 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description for mouse mode 0: no 2X pf capacitor connected to OSC1 (default) 1: has 2X pf capacitor connected to OSC1 0: no 4X pf capacitor connected to OSC1 (default) 1: has 4X pf capacitor connected to OSC1 0: no 8X pf capacitor connected to OSC1 (default) 1: has 8X pf capacitor connected to OSC1 Always read 0 0: no 2X pf capacitor connected to OSC2 (default) 1: has 2X pf capacitor connected to OSC2 0: no 4X pf capacitor connected to OSC2 (default) 1: has 4X pf capacitor connected to OSC2 0: no 8X pf capacitor connected to OSC2 (default) 1: has 8X pf capacitor connected to OSC2 0: no 16X pf capacitor connected to OSC2 (default) 1: has 16X pf capacitor connected to OSC2
Where X is 3pf capacitor. OSC CAP Control Register - OSCC
Rev. 1.00
32
December 15, 2009
HT82K74E/HT82K74EE
Bit No. Fun. Name R/W Description for mouse mode MCU system clock division selection 00: system clock= system oscillator output clock/4 (6.75MHz) 01: system clock= system oscillator output clock/8 (3.3MHz) 10: system clock= system oscillator output clock/16 (1.68MHz) 11: system clock= system oscillator output clock/1 (only for 4MHz) 27MHz oscillator built-in capacitor enable control 0: disable the built-in capacitor connection to both OSC1 and OSC2 (default) 1: enable the built-in capacitor connection to both OSC1 and OSC2 where the built-in capacitors for both OSC1 and OSC2 are defined by the OSC CAP control register OSCC. 27MHz oscillator (OSC) operating mode control 0: OSC operates in normal mode without frequency modulation. 1: OSC operates in frequency modulation mode for RF transmission. 27MHz oscillator (OSC) current control when OSC operates in frequency modulation mode. 0: normal current state is selected when the VDD voltage is equal to or higher than 3V. 1: high current state is selected when the VDD voltage is lower than 3V. Always read 0
0~1
CLK_DIV
R/W
2
CAP_EN
R/W
3
OSC_MOD
R/W
4
I_SEL
R/W
5~7
Reserved bit
R/W
27MHz Oscillator Control Register - RFCTR (21H) Period Timer Register - PTR This register is used to define the period of the timer which always counts in the Power Down Mode. Once the timer is reached, the MCU will be woken-up by Period Timer Register overflow. Once the MCU is woken-up by the period timer, the CNT_WK bit of the wake-up Register is set to 1. Bit No. Function Name R/W Description The Period Timer is the time interval generator with one second as a unit. If the bits [7:0] are equal to 00H, the MCU will be woken up by one of the wake-up source mentioned in Wake-up Section except the PTR overflow event. If the bits [7:0] are not equal to 00H, the MCU will be woken up from the Power Down mode by the following events except WDT overflow event:
* I/O Port wake-up * INT wake-up * Reset * The Period Timer is reached to the values specified by the PTR.
0~7
Period Timer
R/W
Period Timer Register - PTR
Rev. 1.00
33
December 15, 2009
HT82K74E/HT82K74EE
DC-to-DC Converter (DC/DC) This circuit is used to generate a stable 2.8V or 3.0V or 3.3V (error 0.1V) power voltage for the whole device and output to the IRPT. The DC/DC clock frequency is 130kHz. It can also detect the battery voltage. If the battery voltage drops to 2.2V or 2.0V, the choice of which is determined by a configuration option (error 0.1V), the DC/DC circuit will output a Low Voltage Detect signal LVD (2.2V/2.0V Low battery flag stored in LVDF bit of the Control Register CTLR) to the MCU. There is also a low voltage reset (LVR) circuit to check the DC/DC output voltage. When the DC/DC output voltage drops to 2.4V, the MCU will be reset. The LVR function is controlled by a configuration together with a software control bit named DC_ctrl in the Control Register CTLR. To enable the LVR function, the configuration option of LVR function has to be enabled and the control bit DC_ctrl must be set to 0 to enable the DC/DC circuit. If the configuration option is selected to disable the LVR function or the DC_ctrl bit is set to 1 to disable the DC/DC circuit, then the LVR function will be disabled. If the LVR function is enabled by appropriate setting of the configuration option and software control bits as mentioned above, then the LVR still operates even if the MCU enters the Power Down Mode. It is recommended that the LVR function is enabled when the MCU is in the Power Down Mode. As the voltage of the Battery-in pin drops to 2.2V, the DC/DC converter can still operate correctly and is capable of outputting a drive current of at least 50mA.
B A T _ IN DC_O ut T e s t_ D C LX
Amplifier Output for 27MHz The RF_OUT pin is the signal output pin and is sourced from the system oscillator clock output signal via a power amplifier. The RF_OUT impedance is 50 for which the user can design an antenna to transmit the signal. The integrated power amplifier is used to supply power to RF_OUT and can select either 0dBm for full power or -3dBm for half power, via a configuration option. The amplifier can be enabled or disabled using the Amplifier function control bit AMP_ctrl in the Control Register CTLR.
S y s te m O s c illo r C lo c k O u tp u t A M P _ c trl AMP. RF_O U T
This output is use to output the RF signal to the antenna. Output Power= 0dBm (1b) for full, -3dBm for half Load Impedance= 50W The RF-carrier is shifted in frequency according to the data, which is known as Frequency Shift Keying (FSK). The data recognition depends upon the method which the RF receiver uses. The shifted frequency is implemented by the 27MHz oscillator operating mode control bit OSC_MOD in the RFCTR register. When the OSC_MOD bit is set to 1, the oscillator operates in its frequency modulation mode for RF transmission. To achieve frequency modulation, built-in capacitors can be selected which are connected to OSC1 and OSC2 using the built-in capacitor enable control bit CAP_EN in the RFCTR register. If the CAP_EN bit is set to 1, the selected built-in capacitors determined by the oscillator capacitor control register OSCC can be connected to OSC1 and OSC2. If the supply voltage drops lower than 3V when the oscillator operates in its frequency modulation mode, the oscillator current control bit I_SEL in the RFCTR register should be set to 1 to ensure that the oscillator can perform its frequency modulation normally.
D C /D C w ith V o lta g e D e te c to r
2 .4 V L V R 1 .8 V /2 .2 V /2 .5 V /2 .8 V L V D
Output Port used Slew Rate Control I/O Pin The I/O port output delay time of the rising and falling transition is 100ns or 200ns. There is a configuration option bit to define the slew rate of all I/O pins.
Rev. 1.00
34
December 15, 2009
HT82K74E/HT82K74EE
Configuration Options
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Options PA0~PA7 pull-high by bit: pull-high or non-pull-high PA0~PA7 wake-up by bit: wake-up or non-wake-up PB0~PB7 wake-up by nibble: wake-up or non-wake-up PB0~PB7 pull-high by nibble: pull-high or non-pull-high PC0~PC7 wake-up by nibble: wake-up or non-wake-up PC0~PC7 pull-high by nibble: pull-high or non-pull-high PD0~PD7 wake-up by nibble: wake-up or non-wake-up PD0~PD7 pull-high by nibble: pull-high or non-pull-high PE0~PE3 wake-up by nibble: wake-up or non-wake-up PE0~PE3 pull-high by nibble: pull-high or non-pull-high WDT: enable or disable TBHP function: enable or disable DC-DC output voltage: 2.8V, 3.0V, 3.3V LVR: enable or disable LVD voltage: 2.2V or 2.0V I/O Slew Rate: 100ns or 200ns Power Amp: full or half
Application Circuits
1 2 3 4 5 V 100kW 9 10 11 12 13 14 15 VDD 16 0 .1 m F
DD
PA7 PA6 PA5 PA4 6 7 8 PA3 P A 2 /T M R PA1 PA0 RES PC5 PC4 PC3 PC2 PC1 PC0 VDD
P B 0 /V A P B 1 /V B P B 2 /Z A P B 3 /Z B PB4 PB5 PB6 PB7 LX VSSLX B A T _ IN VDD RF_O U T VSS OSC1 OSC2
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 27M Hz 47mF GND V 0 .1 m F
DD
CAP
H T 8 2 K 7 4 E /H T 8 2 K 7 4 E E
Rev. 1.00
35
December 15, 2009
HT82K74E/HT82K74EE
Instruction Set
Introduction C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be CLR PCL or MOV PCL, A. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Logical and Rotate Operations The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Rev. 1.00
36
December 15, 2009
HT82K74E/HT82K74EE
Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the SET [m].i or CLR [m].i instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] INCA [m] INC [m] DECA [m] DEC [m]
Description Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory
Cycles 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 1 1Note 1 1Note
Flag Affected Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
Logic Operation
Increment & Decrement
Rev. 1.00
37
December 15, 2009
HT82K74E/HT82K74EE
Mnemonic Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Description Cycles Flag Affected
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
Rev. 1.00
38
December 15, 2009
HT82K74E/HT82K74EE
Instruction Definition
ADC A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) ADD A,[m] Description Operation Affected flag(s) ADD A,x Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) AND A,[m] Description Operation Affected flag(s) AND A,x Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Rev. 1.00 Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ACC + [m] + C OV, Z, AC, C Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. ACC ACC + [m] OV, Z, AC, C Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ACC + x OV, Z, AC, C Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ACC + [m] OV, Z, AC, C Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND [m] Z Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ACC AND [m] Z 39 December 15, 2009
HT82K74E/HT82K74EE
CALL addr Description Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack Program Counter + 1 Program Counter addr None Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] 00H None Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i 0 None Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF
Operation
Affected flag(s) CLR [m] Description Operation Affected flag(s) CLR [m].i Description Operation Affected flag(s) CLR WDT Description Operation
Affected flag(s) CLR WDT1 Description
Operation
Affected flag(s) CLR WDT2 Description
Operation
Affected flag(s)
Rev. 1.00
40
December 15, 2009
HT82K74E/HT82K74EE
CPL [m] Description Operation Affected flag(s) CPLA [m] Description Complement Data Memory Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] [m] Z Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC [m] Z Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ACC + 00H or [m] ACC + 06H or [m] ACC + 60H or [m] ACC + 66H C Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] [m] - 1 Z Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] - 1 Z Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO 0 PDF 1 TO, PDF
Operation Affected flag(s) DAA [m] Description
Operation
Affected flag(s) DEC [m] Description Operation Affected flag(s) DECA [m] Description Operation Affected flag(s) HALT Description
Operation
Affected flag(s)
Rev. 1.00
41
December 15, 2009
HT82K74E/HT82K74EE
INC [m] Description Operation Affected flag(s) INCA [m] Description Operation Affected flag(s) JMP addr Description Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] [m] + 1 Z Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] + 1 Z Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter addr None Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC [m] None Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC x None Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ACC None No operation No operation is performed. Execution continues with the next instruction. No operation None Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR [m] Z
Operation Affected flag(s) MOV A,[m] Description Operation Affected flag(s) MOV A,x Description Operation Affected flag(s) MOV [m],A Description Operation Affected flag(s) NOP Description Operation Affected flag(s) OR A,[m] Description Operation Affected flag(s)
Rev. 1.00
42
December 15, 2009
HT82K74E/HT82K74EE
OR A,x Description Operation Affected flag(s) ORM A,[m] Description Operation Affected flag(s) RET Description Operation Affected flag(s) RET A,x Description Operation Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR x Z Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ACC OR [m] Z Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter Stack None Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter Stack ACC x None Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter Stack EMI 1 None Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 None Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 [m].7 None
Affected flag(s) RETI Description
Operation
Affected flag(s) RL [m] Description Operation
Affected flag(s) RLA [m] Description
Operation
Affected flag(s)
Rev. 1.00
43
December 15, 2009
HT82K74E/HT82K74EE
RLC [m] Description Operation Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 C C [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 C C [m].7 C Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 None Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 C C [m].0 C Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 C C [m].0 C
Affected flag(s) RLCA [m] Description
Operation
Affected flag(s) RR [m] Description Operation
Affected flag(s) RRA [m] Description
Operation
Affected flag(s) RRC [m] Description Operation
Affected flag(s) RRCA [m] Description
Operation
Affected flag(s)
Rev. 1.00
44
December 15, 2009
HT82K74E/HT82K74EE
SBC A,[m] Description Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] - C OV, Z, AC, C Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] - C OV, Z, AC, C Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] - 1 Skip if [m] = 0 None Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC [m] - 1 Skip if ACC = 0 None Set Data Memory Each bit of the specified Data Memory is set to 1. [m] FFH None Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i 1 None
Operation Affected flag(s) SBCM A,[m] Description
Operation Affected flag(s) SDZ [m] Description
Operation Affected flag(s) SDZA [m] Description
Operation
Affected flag(s) SET [m] Description Operation Affected flag(s) SET [m].i Description Operation Affected flag(s)
Rev. 1.00
45
December 15, 2009
HT82K74E/HT82K74EE
SIZ [m] Description Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] + 1 Skip if [m] = 0 None Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] + 1 Skip if ACC = 0 None Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] OV, Z, AC, C Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] OV, Z, AC, C Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - x OV, Z, AC, C
Operation Affected flag(s) SIZA [m] Description
Operation Affected flag(s) SNZ [m].i Description
Operation Affected flag(s) SUB A,[m] Description
Operation Affected flag(s) SUBM A,[m] Description
Operation Affected flag(s) SUB A,x Description
Operation Affected flag(s)
Rev. 1.00
46
December 15, 2009
HT82K74E/HT82K74EE
SWAP [m] Description Operation Affected flag(s) SWAPA [m] Description Operation Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 [m].7 ~ [m].4 None Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3 ~ ACC.0 [m].7 ~ [m].4 ACC.7 ~ ACC.4 [m].3 ~ [m].0 None Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m] = 0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] Skip if [m] = 0 None Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i = 0 None Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None
Affected flag(s) SZ [m] Description
Operation Affected flag(s) SZA [m] Description
Operation Affected flag(s) SZ [m].i Description
Operation Affected flag(s) TABRDC [m] Description Operation
Affected flag(s) TABRDL [m] Description Operation
Affected flag(s)
Rev. 1.00
47
December 15, 2009
HT82K74E/HT82K74EE
XOR A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) XOR A,x Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ACC XOR [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR x Z
Rev. 1.00
48
December 15, 2009
HT82K74E/HT82K74EE
Package Information
28-pin SSOP (150mil) Outline Dimensions
28 A
15 B
1 C C'
14
G H a F
D E
Symbol A B C C D E F G H a
Dimensions in mil Min. 228 150 8 386 54 3/4 4 22 7 0 Nom. 3/4 3/4 3/4 3/4 3/4 25 3/4 3/4 3/4 3/4 Max. 244 157 12 394 60 3/4 10 28 10 8
Rev. 1.00
49
December 15, 2009
HT82K74E/HT82K74EE
SAW Type 32-pin (5mm5mm) QFN Outline Dimensions
D 25 b E e A1 A3 L A 17 16 24
D2 32 1 E2 8 9 K
Symbol A A1 A3 b D E e D2 E2 L K
Dimensions in inch Min. 0.028 0.000 3/4 0.007 3/4 3/4 3/4 0.049 0.049 0.012 3/4 Nom. 3/4 3/4 0.008 3/4 0.197 0.197 0.020 3/4 3/4 3/4 3/4 Max. 0.031 0.002 3/4 0.012 3/4 3/4 3/4 0.128 0.128 0.020 3/4
Symbol A A1 A3 b D E e D2 E2 L K
Dimensions in mm Min. 0.70 0.00 3/4 0.18 3/4 3/4 3/4 1.25 1.25 0.30 3/4 Nom. 3/4 3/4 0.20 3/4 5.00 5.00 0.50 3/4 3/4 3/4 3/4 Max. 0.80 0.05 3/4 0.30 3/4 3/4 3/4 3.25 3.25 0.50 3/4
Rev. 1.00
50
December 15, 2009
HT82K74E/HT82K74EE
48-pin SSOP (300mil) Outline Dimensions
48 A
25 B
1 C C'
24
G H a F
D E
Symbol A B C C D E F G H a
Dimensions in inch Min. 0.395 0.291 0.008 0.613 0.085 3/4 0.004 0.025 0.004 0 Nom. 3/4 3/4 3/4 3/4 3/4 0.025 3/4 3/4 3/4 3/4 Max. 0.420 0.299 0.012 0.637 0.099 3/4 0.010 0.035 0.012 8
Symbol A B C C D E F G H a
Dimensions in mm Min. 10.03 7.39 0.20 15.57 2.16 3/4 0.10 0.64 0.10 0 Nom. 3/4 3/4 3/4 3/4 3/4 0.64 3/4 3/4 3/4 3/4 Max. 10.67 7.59 0.30 16.18 2.51 3/4 0.25 0.89 0.30 8
Rev. 1.00
51
December 15, 2009
HT82K74E/HT82K74EE
48-pin LQFP (7mm7mm) Outline Dimensions
C D 36 25 G H
I 37 24
F A B E 48 13 K 1 12 a J
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 8.90 6.90 8.90 6.90 3/4 3/4 1.35 3/4 3/4 0.45 0.10 0 Nom. 3/4 3/4 3/4 3/4 0.50 0.20 3/4 3/4 0.10 3/4 3/4 3/4 Max. 9.10 7.10 9.10 7.10 3/4 3/4 1.45 1.60 3/4 0.75 0.20 7
Rev. 1.00
52
December 15, 2009
HT82K74E/HT82K74EE
Product Tape and Reel Specifications
Reel Dimensions
T2 D
A
B
C
T1
SSOP 28S (150mil) Symbol A B C D T1 T2 SSOP 48W Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.01.0 100.00.1 13.0
+0.5/-0.2
Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness
Dimensions in mm 330.01.0 100.01.5 13.0
+0.5/-0.2
2.00.5 16.8
+0.3/-0.2
22.20.2
2.00.5 32.2
+0.3/-0.2
38.20.2
Rev. 1.00
53
December 15, 2009
HT82K74E/HT82K74EE
Carrier Tape Dimensions SSOP 28S (150mil)
P0 D
E F W C
P1
t
B0
D1
P A0
K0
R e e l H o le p a c k a g e p in 1 a n d th e r e e l h o le s a r e lo c a te d o n th e s a m e s id e . IC
Symbol W P E F D D1 P0 P1 A0 B0 K0 t C
Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width
Dimensions in mm 16.00.3 8.00.1 1.750.1 7.50.1 1.55 1.50
+0.10/-0.00 +0.25/-0.00
4.00.1 2.00.1 6.50.1 10.30.1 2.10.1 0.300.05 13.30.1
Rev. 1.00
54
December 15, 2009
HT82K74E/HT82K74EE
SSOP 48W
D
E F W C B0
P0
P1
t
D1
P K2 A0
K1
R e e l H o le ( C ir c le ) p a c k a g e p in 1 a n d th e r e e l h o le s a r e lo c a te d o n th e s a m e s id e . R e e l H o le ( E llip s e ) IC
Symbol W P E F D D1 P0 P1 A0 B0 K1 K2 t C
Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Cavity Depth Carrier Tape Thickness Cover Tape Width
Dimensions in mm 32.00.3 16.00.1 1.750.10 14.20.1 2 Min. 1.50
+0.25/-0.00
4.00.1 2.00.1 12.00.1 16.20.1 2.40.1 3.20.1 0.350.05 25.50.1
Rev. 1.00
55
December 15, 2009
HT82K74E/HT82K74EE
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2009 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
56
December 15, 2009

▲Up To Search▲

Price & Availability of HT82K74E

	To Download HT82K74E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .